1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel technique to simplify the manufacture process for a substrate of memory chip module with chip layout placing the bonding pads in the center portion of the chip. Furthermore, the substrate-on-chip chip modules are assembled as CSP-ready multiple-chip-module (MCM) packaging configuration. The assembling and testing processes of this CSP ready MCM are simplified to achieve a lower production cost. Furthermore, the procedures to repackage and utilize the know-good-die (KGD) packaged as a known-good-CSP (KGCSP) after testing is also simplified such that an effective method is provided to minimize the wastes of the known-good-dice.
2. Description of the Prior Art
There is a concern in applying the surface mount technology (SMT) to electronic package that package cracking, e.g., a pop corning phenomenon, may occur upon board mounting. This is generally caused by permeation of moisture through the plastic package body. In order to prevent this pop-corning phenomenon, very stringent requirements are imposed for SMT package design, materials, processes, dry packing, and qualification tests to prevent package cracks and to assure package reliability. FIG. 5 shows an example of such requirements for a SMT package. Time for production and costs are increased due to processes taken to satisfy these requirements. Examples of such packages are disclosed as that in U.S. Pat. No. 5,684,330, where the entire packaging structure is encapsulated with plastic molding. This type of packaging configuration is also implemented for most of the dynamic ransom access memory (DRAM) chips where the bonding pads are placed in the central portion of the chip. For the purposes of improving electrical performance and minimizing packaging width, a lead-on-chip (LOC) technology is applied. Each individual package is tested and burned in and good packages are then surface mounted on a module substrate in DIMM or PCMCIA format with edge connectors for socket applications. Examples of electronic packages are disclosed in U.S. Pat. No. 5,346,861 by Khandros et al., U.S. Pat. No. 5,068,712 by Murakami et al., and U.S. Pat. No. 4,862,245 by Pashby et al. As plastic molding of the entire structure is shown for these patented packaging assemblies, the difficulties of applying more elaborate stringent requirements for assembling and testing the packages are not resolved by these patented package configurations.
Furthermore, there is a different challenge faced by those applying the multiple-chip-module (MCM) technology to package multiple electronic chips into a single module. This challenge arises from the fact that a MCM module can function properly only if every chip assembled into this MCM package is individually a good die. Also, due to the accumulative effect, even a small percentage of reject rate for the individual chips, an unacceptable loss to the MCM packages is generated in using these chips. For example, a 99% chip acceptance rate for the individual chips, when assembled into eight-chip modules (X8 modules) as dual in-line memory module (DIMM) or single-in-line-memory module (SIMM) packages, an 8% loss or rework rate is generated which is clearly unacceptable.
In order to reduce wastes of resources committed to packaging chips which are not good dice, burn-in tests of individual chips are performed again after a wafer probe operation to identify the known good dice (KGD) before a MCM packaging processes are carried out. However, the processes for burning-in each individual chip or chip-size package (CSP) are very expensive due to the requirements of special testing sockets, and large dedicated burn-in board. Furthermore, difficult handling techniques are required to test these individual chips. Due to these special and expensive requirements for qualifying an integrated circuit (IC) chip as a known good die (KGD), it generally costs more to test a chip than to test a package. For the same reasons, the price of a known good die is approximately two to three times as that of a untested die. Even with the high cost of testing and a much higher price to use the KGD, due to the concern of accumulative losses when chips are assembled as multiple chip modules, there is no choice but to employ the KGDs.
In addition to the costs related to the requirement of using the chip size packages, two level of substrates or lead frames are employed in conventional multiple chip modules wherein known good dice contained in a CSP are assembled. The first level of substrate is used for packaging individual chips. The multiple chip module substrate is a second level substrate, which is used for mounting multiple chips each packaged in a CSP module. Additional costs are incurred in this two level substrate structure since it requires more material and processing. This two-level substrate structure further presents another disadvantage that the packages have a higher profile and higher thermal resistance causing poor heat dissipation. In order to enhance device miniaturization, more and more modern applications implemented with packaged electronic chips require a reduced thickness. Conventional MCM packages implemented with a two-level substrate structure have very limited usefulness in modern miniaturized devices when an electronic packages with a very small thickness are required.
Therefore, a need still exits in the art to provide an improved configuration and procedure for testing and packaging the multiple chip modules to reduce the cost of testing. The need also exists for a new configuration to more conveniently and economically reuse the known good dice when a known good die is packaged with other failed chips into a multiple-chip-module. There is further a need to provide an improved packaging configuration, particularly for the SMT packages with pop-corning difficulties, such that the packaging and testing requirements can be relaxed to shorten the production time and reduce the production costs without degrading the product reliability.